1. Field of the Invention
The invention relates to an overlay mark, capable of solving the problem of alignment measurement caused by low step height of the outer mark.
2. Description of the Related Art
In addition to the control of critical dimension (CD), factors for a successful photolithography process on a wafer include alignment accuracy (AA). Therefore, the measurement of accuracy, that is, the measurement of overlay error is crucial to the semiconductor fabrication process. An overlay mark is used as a tool for measuring overlay error and to determine whether the photoresist pattern is precisely aligned with the previous wafer layer on a wafer after a photolithography process.
Conventionally, the overlay marks are located on the corners of the edge of each chip to measure whether the photoresist pattern is aligned with the previous wafer layer in the fabrication process.
FIGS. 1A to 1C are cross sectional views illustrating a method of fabricating a metal interconnect having a via (via 0) and an overlay mark. Referring to FIG. 1, a substrate 100 is provided, wherein the substrate 100 includes a chip region 102 and an overlay mark region 104. The dielectric layer 106a is formed on the substrate 100, and then the dielectric layer 106a is patterned to form a contact hole 108 in the dielectric layer 106a on the chip region 102. The subsequent process is another contact formation step, rather than a wire line forming step, so that no overlay mark is formed in the dielectric layer 106a on the overlay mark region 104.
As shown in FIG. 1A, the contact hole 108 is filled with tungsten 107a, and then a dielectric layer 110a is formed on the dielectric layer 106a. Thereafter, the dielectric layer 110a is patterned to form a via hole (via 0) in the dielectric layer 110a on the chip region 102 and a trench 114 in the dielectric layer 110a on the overlay mark region 104 simultaneously, wherein the trench 114 serves as a outer mark. Subsequently, a tungsten layer 116 is formed on the dielectric layer 110a to fill into the via hole and trench 114.
Referring to FIG. 1B, a chemical mechanical polishing process is performed on the tungsten layer 116 (in FIG. 1A) until the dielectric layer 110a is exposed to form a via (via 0) 112 on the chip region 102 and leave tungsten layer 116a in the trench 114 on the overlay mark region 104.
Referring to FIG. 1C, a metal layer 118 is formed on the substrate 100 for forming wire lines. A patterned photoresist layer 120 is formed on the metal layer 118. The portion of the patterned photoresist layer 120 on the chip region 102 serves as a mask for defining wire lines, and the other portion of the patterned photoresist layer 120a on the overlay mark region 104 serves as inner mark.
In general, the dielectric layer 110a used for forming via hole (via 0) is thinner than the dielectric layer 106a, so that the trench 114 is mostly filled with the metal layer 116a after performing the chemical mechanic polishing process. Therefore, when the overlay mark is used to measure the alignment accuracy, the peak signal t of the outer mark can not be read because of low step height on the outer mark. Consequently, the overlay error can not be calculated.